This invention relates generally to digital signal sampling techniques, and more specifically to such techniques as implemented in logic analyzers and other test equipment.
Logic analyzer instruments are widely used to test and analyze the operation of digital circuitry by simultaneously acquiring a large number of samples of logic signals at different points within the digital circuitry. An example of such digital circuitry is a portion of a mainframe computer. The logic analyzer instrument has a number of conductors, such as from 4 to 50, which are provided at their ends with individual connectors or probes for attachment to different circuit points within the digital system being tested. Each logic signal has only high or low voltage levels. All logic signals being recorded by the logic analyzer are periodically and simultaneously sampled by the logic analyzer to determine whether they are high or low at each sample time. This information is stored in a digital memory and used to reconstruct the waveforms, which are then displayed for analysis by the technologist who is conducting the test.
A primary purpose of such a test is to determine the relative time relationship of logic signals at the different circuit points to which the logic analyzer is connected within the system or device under test. That is, it is the relative times of the transition of the various logic signals between their high and low states that is analyzed. The determination of the interval between the time that certain of these acquired logic signals change state is useful in testing or evaluating digital hardware parameters, such as propagation delay, channel-to-channel-skew, setup time, and hold time. Another use for a logic analyzer is to record the states of various logic signals when they are known to be stable. Such logic state relationships, usually representing addresses or data words, are important in software analysis.
In any application, the logic analyzer has a finite memory which continually records samples of the logic signals being acquired until a triggering event occurs. Such a triggering event can be set to occur in response to a particular combination of the logic signals, some arbitrary time or event, and the like.
Present logic analyzers develop a sampling clock signal in one of two distinct ways. One way is simply to connect the instrument to the internal clock of the system under test, either by a direct connection or by deriving the clock from the acquired signals being analyzed. The logic signals are then sampled at a rate equal to the clock frequency of the system under test. The other way is to generate the clock signal within the instrument that is independent of and asynchronous to the logic signals of the system under test. In either case, the instrument can only determine for each logic signal acquired that a signal level has changed in an interval between two consecutive samples. The higher frequencies now used in computer system clocks, and the current use of multiple phase clocks, require increased sampling rates in order to improve the resolution of the acquired information. The asynchronous technique has been utilized by increasing the frequency of the instrument's internal clock. This approach is, however, reaching the limit of the instrument's circuit speed, and is quite costly to implement.
Therefore, it is a primary object of the present invention to further increase the resolution of existing logic analyzer instruments.